IEEE 696 Bus

Introduction

By Robert Weatherford

After going on an archaeological expedition, I found it interesting to see how the final IEEE 696 standard in 1983 (otherwise known as the S-100 bus) evolved. Most enthusiasts know the story of the beginnings of the S-100 bus, but for those who may not know, here’ a brief history. Ed Roberts of MITS designed the Altair 8800 in 1974 with 100-pin plug-in cards, pretty much just putting buffered 8080A signals onto the bus. An article in Popular Electronics magazine was written about it in January 1975, and it became an instant hobbyist hit. So much so, that it created a market far beyond the capacity of any one company to serve. IMSAI was the first company to “clone” the computer. They did a better more industrial design (and a bit more expensive), but demand was still outstripping their capacity to come out with expansion cards. Many new companies sprung up to fill the demand for RAM, different processors, cassette and disk interfaces, and various I/O cards. Many releases included their own proprietary extensions of the bus by necessity. By late 1976, IMSAI had added four new address lines and phantom lines to support their “Megabyte Micro” campaign. Things were getting a little bit out of hand. The term “S-100 compatible” was becoming almost a joke as Morrow, MITS, and IMSAI cards were not really all that compatible.

Today, the IEEE 696-1983 standard is Inactive-Withdrawn. Oddly, it is still for sale on the IEEE website and others. I am probably breaking all kinds of laws by including a copy of the standard here.

As a former IMSAI employee, much of my view of the S-100 bus evolution is admittedly colored by my experience. I welcome other experiences, viewpoints, and information.

First Draft

In May 1978, Computer magazine published “PROPOSED STANDARD FOR THE S-100 BUS, Preliminary Specification, IEEE Task 696.1/D2.” This was the first known attempt to get things under control. Among the more notable changes were:

Bus Signal Changes

• Pin 12 (XRDY2) was removed and made unspecified.
• Pins 13 through 17 were unspecified. IMSAI had begun using these pins for extended addressing.
• Pin 20 (UNPROT) was removed and made unspecified. IMSAI used this for memory unprotect.
• Pin 21 (SS) was removed and made unspecified. IMSAI also called this pin /DIDSBL (Data In Disable).
• Pin 25 (Φ1) was removed and made unspecified.
• Pin 27 (PWAIT) was retained. The final draft removed it.
• Pin 53 (/SSWDSB) was removed and made unspecified.
• Pins 55 through 58 and 60 were unspecified. MITS used these lines for various purposes.
• Pins 59 and 61 (/SXTRQ and /SIXTN) were added to support 16-bit data transfers.
• Pin 67 (/PHANTOM) was added to disable normal slaves and enable phantom slaves. IMSAI had assigned A19 to this pin and used it and A16 (pin 16) as their standard phantom line.
• Pins 69, 70, and 71 (/PS, PROT, RUN) were removed and made unspecified.
• Pin 98 (SSTACK) was removed and made unspecified.

Bus Protocol Changes

• The address and status signals of basic I/O operations were latched on the rising edge of Φ2 in the middle of bus cycle 2 (while PSYNC is still high).
• The removal of the Φ1 signal would break many existing cards, as they used the trailing edge of (PSYNC ∧ Φ1) to latch address and status.
• The 16-bit data bus protocol using the new /SXTRQ and /SIXTN signals was introduced and survived unchanged to the final draft.
• The bus signal electrical specifications were introduced and survived unchanged to the final draft.
• The extended address bits A16 through A23 are multiplexed on the DO lines. They must occur as shown within 250 ns after the rising edge of Φ2 during BS₁.
• The committee is currently considering proposals for DMA and interrupt priority specifications. These will be made public in the near future-perhaps at the NCC meeting.

Second Draft

In July 1979, the second draft was published in Computer magazine. It fleshed out the DMA arbitration protocol as well as implementation of the extended addressing with the addition of eight parallel address lines with the same timing as A0 through A15.

Bus Signal Changes

• Pin 12 became the NMI* signal.
• Pin 13 became the PWRFAIL* signal.
• Pins 14, 57, 56, and 55 became the TMA3*, TMA2*, TMA1*, and TMA0* signals for TMA (DMA) arbitration.
• Pins 64, 63, 62, 61, 59, 15, 17, and 16 became the A23, A22, A21, A20, A19, A18, A17, and A16 signals.
• Pins 20, 53, and 70 became an additional 0V (ground) signal.
• Pin 25 became the pSTVAL* signal. This was originally the Φ1 signal and was removed by the first draft.
• Pin 27 (pWAIT) was removed and made RFU. This decision breaks several IMSAI cards that use pWAIT in their wait-state generation logic.
• Pins 58 and 60 (sXTRQ* and SIXTN*) were moved from pins 59 and 61 in the second draft.
• Pin 98 became the ERROR* signal.

Bus Protocol Changes

• With the reintroduction of the Φ1 signal (now called pSTVAL*), the address and status signals of basic I/O operations are latched on the trailing edge of pSTVAL* in the middle of bus cycle 2 (while PSYNC is still high). This change allows the address and status signals to be latched earlier if the CPU supports it. This “unbreaks” the cards previously broken by the first draft.
• The extended address multiplexing protocol was eliminated.
• The DMA arbitration protocol was fully specified.

Final Draft

In September 1983, the final standard was released by IEEE. It is practically identical to the second draft was published in 1979. The two semantic changes were (quoting the document):

1. In the main, changes to the original consist of editorial changes to clear up ambiguities. The major technical change involves how we think about 8- and 16-bit bus transfers, rather than how the mechanism works electrically. To go along with this change in thinking, some new nomenclature was agreed upon.
2. There was one other change in the nomenclature, and that concerns the renaming of the term DMA (Direct Memory Access) to TMA (Temporary Master Access).

IEEE 696 Bus Design Data

Much of our S-100 design data lives here.

Overclocking

The spec states that the clock frequency shall be between 500 kHz and 6 MHz. Fortunately, many of the bus timing parameters are based on the clock period, so some amount of scaling is possible. There are a few absolute parameters whose values are 70 and 80 nanoseconds. Without diving into the details, this would seem to probably limit tCY to 100 nS, or 10 MHz. Some late-model S-100 cards sport 12MHz bus speeds. For permanent bus masters, Parastream will design to and claim no more than a 10 MHz bus, and always provide a default no more than 6 MHz. For temporary bus masters and bus slaves, Parastream will operate with a clock frequency of up to 10 MHz (zero wait state is not guaranteed).  Due to our conservative design approaches, acheiving 12 MHz or higher may be possible, but we will never guarantee it.

Logic Families and Bus Interfacing

Bus input signals may use only the 74AS, 74ALS, and 74LS families. The 74LS family remains the workhorse, but the 74ALS family excels when you need to have an unbuffered bus fan-in of up to 4 loads. The 74AS family is for speed-critical circuits where the extreme power consumption is tolerable. Bus input signals need to be tolerant of noise. Using schmitt trigger devices is always a good idea.

Bus output signals should use drivers with short propagation delays, but rise and fall times of greater than 5ns. The 74LS244 is a great example of a good bus driver.

For all bus signals, the devices on the signal should be as physically close to the connector as possible to lessen the transmission line effects.

For internal logic, the 74F family is the best speed/power trade-off for high-speed logic. The 74AS family is faster but at nearly twice the power. The 74S family is good for high fanout, but it is extremely power-hungry.

The most cost-effective families are 74LS and 74F.